1. Field of the Invention
The present invention generally relates to an interface circuit, and more particularly, to a capacitance interface circuit.
2. Description of Related Art
FIG. 1 is a circuit diagram of a capacitance interface circuit 100 disclosed in U.S. Pat. No. 6,452,514. FIG. 2 is an operation timing diagram of the capacitance interface circuit 100 in FIG. 1. Referring to both FIG. 1 and FIG. 2, the capacitance interface circuit 100 includes a sampling switch 101, a reset switch 103, a control means 105, a measurement means 107, a charge cancellation means 109, a buffer B, and capacitors Ci and Cs. In the capacitance interface circuit 100, the capacitor Cs is first reset according to a reset signal RES. Then, the capacitor Ci is charged. Next, charges stored in the capacitor Ci are conducted/transferred into the capacitor Cs through charge pump means. Finally, the charges stored in the capacitor Cs are measured to determine the capacitance of the capacitor Ci.
It should be mentioned herein that the charges accumulated in the capacitor Cs form the output voltage Vout of the capacitance interface circuit 100. As shown in FIG. 2, the charges in the capacitor Cs are accumulated at each rising edge of a signal received at the end Tx of the capacitor Ci. The voltages V1-VN corresponding to the charges accumulated by the capacitor Cs during each period (i.e., each rising edge can be considered as a period) have following values:V1=Vp*Ci/(Ci+Cs);V2=Vp*Ci/(Ci+Cs)*[1+Cs/(Ci+Cs)];V3=Vp*Ci/(Ci+Cs)*{[1+Cs/(Ci+Cs)+[Cs/(Ci+Cs)]^2];V4=Vp*Ci/(Ci+Cs)*{[1+Cs/(Ci+Cs)+[Cs/(Ci+Cs)]^2+[Cs/(Ci+Cs)]^3];. . . ; andVN=Vp*Ci/(Ci+Cs)*{[1+Cs/(Ci+Cs)+[Cs/(Ci+Cs)]^2+[Cs/(Ci+Cs)]^3+ . . . +Cs/(Ci+Cs)]^(N−1)],wherein Ci is the capacitance of the capacitor Ci; Cs is the capacitance of the capacitor Cs; and Vp is a positive reference voltage of the signal received at the end Tx of the capacitor Ci.
Accordingly, different amount of charges are accumulated by the capacitor Cs during each period (i.e., (V2−V1)≠(V3−V2)≠(V4−V3)≠ . . . ≠(VN−VN−1)). Thus, in order to make the capacitor Cs to accumulate the same or similar amount of charges during each period, the capacitance of the capacitor Cs has to be designed to be much greater than that of the capacitor Ci. However, such a design makes it difficult to dispose the capacitor Cs in an integrated circuit (IC).